In the course of Integrated Circuit (IC) development, functional density (i.e., the number of interconnected electrical components per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process has been made possible by the development of multiple-exposure or multiple-patterning technologies for even finer spatial resolution of a layer. Meanwhile, this scaling down process has also been made possible by the development of Electronic Design Automation (EDA) tools, such as automated placing electrical components and routing corresponding conductive lines, to assist circuit engineers handling the increased complexity of ICs.